The last time I played this little puzzle was with a Lattice FPGA and a DDR2 chip. Started by reading the Micron specification for the DDR2 chip, and then began writing. It was lots of fun, got the chip working, learned a huge amount in the process, and inevitably switched over to Lattice's hard-core DDR2 controller.
Now I've started again, a new journey, to write a DDR3 controller. I purchased Xilinx's ML605 (pricey to say the least). It comes with a Virtex 6 LX240T and a Micron DDR3 SODIMM. It also comes with a built-in JTAG to USB, and Xilinx's ISE Logic Edition.
Armed with Micron's specification, lots of patience, and an abundance of curiousity, I began reading. As a software programmer turned hardware engineer, the ODT and calibration sections were the hardest for me to understand. That caused a long delay in my plans, as it is difficult for me to begin writing without a fairly complete understanding of what I'm doing. Problem was finally solved (at least to my satisfaction) after some Rtt Nom vs Rtt Wr questions were answered by a colleague.
and: http://ionipti.blogspot.com/2010/07/ddr3-fly-by-topology-and-write-leveling.html
Now, down to writing. This board comes with a reference design for a DDR3 controller. From the reference design I took the values for DDR3 Output Strength, DDR3 Rtt Nom, DDR3 Dynamic ODT, and all of the pins' IO specifications. Since I'm not a board designer, I had no way to figure that stuff out on my own, or at least not this time around...
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