Here is an example:
DIFF_SSTL15_T_DCI = IOBUFDS_DIFF_OUT
IOBUFDS_DIFF_OUT took a while to find as it doesn't appear in the Virtex 6 HDL Libraries Guide. It does appear in the Virtex 6 FPGA SelectIO Resources User Guide (ug361.pdf) with a caveat that it is for experienced Xilinx designers for usage in DDR2 / DDR3 applications.
I have yet to figure out why you need a separate tristate for this primitive, but hopefully I'll find that answer as I move along on this project.
Note: When you use a DCI IO standard, you must adhere to the DCI rules. For the ML605, you have to put the CONFIG_CASCADE constraint in so that ISE will successfully generate the bitstream:
//For ML605
CONFIG DCI_CASCADE = "36 35";
CONFIG DCI_CASCADE = "26 25";
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