IO standards vs instantiated primitives

As I said in the previous post, I took the IO specifications from the reference design included with the ML605. What I wasn't expecting was that these IO specifications have to work with specific Xilinx primitives.

Here is an example:
DIFF_SSTL15_T_DCI = IOBUFDS_DIFF_OUT

IOBUFDS_DIFF_OUT took a while to find as it doesn't appear in the Virtex 6 HDL Libraries Guide. It does appear in the Virtex 6 FPGA SelectIO Resources User Guide (ug361.pdf) with a caveat that it is for experienced Xilinx designers for usage in DDR2 / DDR3 applications.

I have yet to figure out why you need a separate tristate for this primitive, but hopefully I'll find that answer as I move along on this project.

Note: When you use a DCI IO standard, you must adhere to the DCI rules. For the ML605, you have to put the CONFIG_CASCADE constraint in so that ISE will successfully generate the bitstream:

//For ML605

CONFIG DCI_CASCADE = "36 35";

CONFIG DCI_CASCADE = "26 25";

First steps

The last time I played this little puzzle was with a Lattice FPGA and a DDR2 chip. Started by reading the Micron specification for the DDR2 chip, and then began writing. It was lots of fun, got the chip working, learned a huge amount in the process, and inevitably switched over to Lattice's hard-core DDR2 controller.

Now I've started again, a new journey, to write a DDR3 controller. I purchased Xilinx's ML605 (pricey to say the least). It comes with a Virtex 6 LX240T and a Micron DDR3 SODIMM. It also comes with a built-in JTAG to USB, and Xilinx's ISE Logic Edition.

Armed with Micron's specification, lots of patience, and an abundance of curiousity, I began reading. As a software programmer turned hardware engineer, the ODT and calibration sections were the hardest for me to understand. That caused a long delay in my plans, as it is difficult for me to begin writing without a fairly complete understanding of what I'm doing. Problem was finally solved (at least to my satisfaction) after some Rtt Nom vs Rtt Wr questions were answered by a colleague.

See: http://ionipti.blogspot.com/2010/07/help-ddr3-odt-on-die-termination.html

and: http://ionipti.blogspot.com/2010/07/ddr3-fly-by-topology-and-write-leveling.html

Now, down to writing. This board comes with a reference design for a DDR3 controller. From the reference design I took the values for DDR3 Output Strength, DDR3 Rtt Nom, DDR3 Dynamic ODT, and all of the pins' IO specifications. Since I'm not a board designer, I had no way to figure that stuff out on my own, or at least not this time around...